1. Field of the Invention
The present invention relates generally to the field of electrically erasable programmable non-volatile memory devices. More particularly, the present invention relates to a method for programming one-bit-per-cell or single-bit storage SONOS type memory cells.
2. Description of the Prior Art
Nitride-based non-volatile memories such as Nitride Read-Only-Memory (NROM), Metal-Oxide-Nitride-Oxide-Silicon (MONOS) type or Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) type non-volatile memory devices, which have traditionally been used to store a single digital bit per memory cell (hereinafter referred to as single-bit storage), are known in the art. Generally, a nitride-based non-volatile memory cell is constructed having a non-conducting dielectric layer, typically a silicon nitride layer, sandwiched between two silicon dioxide layers. The non-conducting dielectric layer functions as an electrical charge-trapping medium. A conductive gate layer is placed over the upper silicon dioxide layer. Buried doping regions or buried bit lines are implanted into the substrate, which function as a buried drain or buried source for a selected memory cell. For single-bit storage SONOS type non-volatile memory, the electrical charge is trapped and localized near a side that is used as the buried drain.
FIG. 1 schematically illustrates an enlarged cross-sectional view of a prior art single-bit storage SONOS type memory cell 100. Typically, single-bit storage SONOS type memory cell 100 is programmed by injecting hot electrons from a portion of the substrate 10, such as the channel section 16 near the buried drain region 12, to the charge-trapping medium 24. Electron injection causes the accumulation of negative charge in the charge-trapping medium 24 that is sandwiched between the bottom oxide layer 22 and the top oxide layer 26. The injection mechanism can be induced by grounding the buried source region 14 and a bulk portion of the substrate 10 and applying a relatively high positive voltage to the control electrode 30 to create an electron attracting field and applying a positive high voltage to the buried drain region 12 in order to generate hot electrons. After sufficient negative charge accumulates on the charge-trapping medium, the negative potential of the charge-trapping medium raises the threshold voltage of its field effect transistor (FET) and inhibits current flow through the channel region through a subsequent read mode. The magnitude of the read current is used to determine whether or not a SONOS type memory cell is programmed. The single-bit storage SONOS type memory cell 100 is typically erased by Fowler-Nordheim (FN) tunneling hot hole injection.
However, the above-described prior art method for programming the single-bit storage SONOS type memory cell 100 has at least one drawback. Since the injected electrons are localized near the drain side, the distribution of the trapped electrons within the charge-trapping medium 24 is therefore asymmetric and non-uniform across the channel region 16 between the source side and drain side of the memory cell 100. The asymmetric electron distribution profile 60 as specifically depicted in an upper portion of FIG. 1 leads to inadequate erasure and thus causes significant threshold voltage (Vt) increase. Accordingly, there is a need to provide an improved programming method to solve this problem.